The present invention relates to computers in general, and more particularly to a method of operating a computer system and to a multiprocessor system which employs such method.
There have already been proposed various methods for use in systems including at least one structural component which initiates the data transfer and at least two receiving structural components for coordinating and assuring data transfer from the structural component that had initiated the data transfer to the receiving structural components. Particular problems are encountered when, at a later point in time, an originally receiving structural component is to be capable of initiating the transfer of data, and a structural component which had originally initiated the transfer of data is to be capable of receiving the data being transferred.
Such problems are encountered, for example, in multiprocessor systems. In this context, it is to be mentioned that there are huge differences between so-called network systems and true multiprocessor systems. In network systems, there has been proposed a multitude of different solutions, of which the so-called C SMA-CD method and the token-passing method are the methods that are known best. What is common to these two methods is that only one structural component is able to transmit and only one structural component is able to receive at any given instant of time. However, as a result of the high speed of transmission in the network, there is created the impression that the data transmission is simultaneous, when the time requirements are not too critical. In the C SMA-CD method, the structural component that is ready to transmit data initially examines whether or not any other transmission is already taking place. If the transmission paths are free, the transmission starts at once. If a conflict or collision nevertheless arises between two transmissions, both of such transmissions are interrupted and a new attempt at transmission is made. The time instant at which the transmission is attempted again is determined by a random number generator. In this manner, it is intended to reduce the possibility or probability that a conflict or collision would occur again between the two restarted transmissions. In performing the token-passing method, a defined bit pattern is passed from one of the structural components to the next. A structural component that is ready to transmit takes the token over and thus indicates the transmission path as being occupied. The data to be transmitted are attached to the token and transmitted to a receiving structural component. The token is transported from one of the structural components to another within a predetermined time grid.
These methods cannot be used in the aforementioned true multiprocessor systems which are usually spatially rigidly connected with one another, inasmuch as they could result in a time behavior that would be critical in the real time domain. Furthermore, expensive measures must be resorted to when two structural components, which can consist, for instance, of input/output modules or of processor modules, are to receive the available data simultaneously. Under these circumstances, there are usually being used time-staggered transmissions, wherein the transmission control proper is performed, for example, by a module capable of directly accessing a register, which is also known as the DMA module. It is further known to utilize in true multiprocessors so-called bus-arbiter modules in order to avoid clashes or collisions between the transmission when more than one structural module is ready to transmit.
A further problem resides in the fact that the receiving structural component is not capable to receive data at any arbitrarily chosen instant of time. For this reason, there must be conducted testing for the occurrence of transmission errors. One solution to this problem would be to conduct the transmission in an interrupt-controlled fashion. However, in systems including at least two processors, this approach requires that the software which is already very close to hardware must be of such a type as to be reentrant; this requires an increased programming expenditure. Moreover, the number of the possible interrupt lines is, as a rule, limited. Therefore, when it is desired that a greater number of the structural components than that of the available interrupts is to be capable of receiving simultaneously, it is no longer possible to utilize this method.
Furthermore, there is known from a book by Andrew S. Tannenbaum entitled "Structured Computer Organization", Prentice-Hall Inc., Englewood Cliffs, N.J., 1984, especially from pages 103 to 110, and from a book by Walter A. Triebel and Avtar Singh entitled "16 Bit Microprocessors", Prentice-Hall Inc., Englewood Cliffs, N.J., 1985, especially pages 317 to 339, a method and a processor system in which a structural component that initiates the transfer of data transfers such data to individually addressable receiving structural components, wherein the accomplishment of the data transfer is acknowledged by a feedback signals. However, the addressing of the receiving structural components must take place at different times, since otherwise clashes would occur in the bus system between the individual transmissions.